This disclosure relates to the polishing of magnetic, optical, semiconductor and silicon wafers and more particularly, to polishing compositions and methods for polishing and planarizing silicon wafers.
The semiconductor industry uses interconnect metals in forming integrated circuits on semiconductor wafers. These interconnect metals are preferably non-ferrous metals. Suitable examples of such non-ferrous interconnects are aluminum, copper, gold, nickel, and platinum group metals, silver, tungsten and alloys comprising at least one of the foregoing metals. These interconnect metals have a low electrical resistivity. Copper metal interconnects provide excellent conductivity at a low cost. Because copper diffuses into many dielectric materials, such as silicon dioxide or doped versions of silicon dioxide, integrated circuit fabricators typically apply a diffusion barrier layer to prevent the copper diffusion into the dielectric layer. For example, barrier layers for protecting dielectrics include, tantalum, tantalum nitride, silicon nitride, tantalum-silicon nitrides, titanium, titanium nitrides, titanium-silicon nitrides, titanium-titanium nitrides, titanium-tungsten, tungsten, tungsten nitrides and tungsten-silicon nitrides.
In the manufacturing of semiconductor wafers, polishing compositions are used to polish semiconductor substrates after the deposition of the metal interconnect layers. Typically, the polishing process uses a “first-step” slurry specifically designed to rapidly remove the excessive interconnect metal. The polishing process then includes a “second-step” slurry to remove the barrier layer. The second-step slurry selectively removes the barrier layer without adversely impacting the physical structure or electrical properties of the interconnect structure. In addition to this, the second step slurry should also display low erosion for dielectrics.
While the “two-step” slurry generally performs satisfactorily in present conditions, it is desirable to have polishing compositions that can be used for planarizing the metal interconnect without substantial dishing of the interconnect metal and scratching of the wafer surface.
Preparation and evaluation of chemically modified abrasives for chemical mechanical polishing by Partch et al. in an abstract presented at Materials Research Society (MRS) meeting in 2001, discloses coating individual particle cores with a layer of organic or inorganic material. However, Partch et al., disclosed manufacturing the polishing composition with abrasive particles having a large particle size distribution that resulted in scratching and other forms of surface damage.
U.S. Pat. Pub. No. 2004/0060502 to Singh discloses a plurality of particles that may be coated by weakly or strongly adsorbing surfactants or polymer additives to a core particle. The polymers thus adsorbed onto the abrasive particles can desorb from the particles during the polishing process to alter polishing characteristics and possibly result in damage to the polished surface.
There thus remains an unsatisfied demand for a method of manufacturing polymer-coated particles suitable for chemical mechanical polishing of magnetic, optical, semiconductor or silicon substrates.